The progress of semiconductor fabrication technology and the upgrade of electrical functionality of chips contribute to the development of semiconductor devices having small IC (integrated circuit) area and high density of contacts, such as ball grid array (BGA) package, flip-chip package, chip size package (CSP) and so on, which are widely applied in portable electronic devices.
For flip-chip packaging technology, normally solder bumps are formed on contacts (e.g. bond pads) of a semiconductor substrate such as a wafer or chip, and the semiconductor substrate is electrically connected to a carrier such as a substrate via the solder bumps. The flip-chip technology advantageously provides a shorter circuit path and better electrical quality as compared to a conventional wire-bonding method. In the flip-chip package structure, the chip may further have an exposed back side, thereby improving heat dissipating efficiency of the chip.
Further, a UBM (under bump metallurgy) structure is formed on the bond pads of the chip before mounting the solder bumps on the bond pads, in order to firmly bond the solder bumps to the chip via the UBM structure. However, due to profile miniaturization and high integration of the chip, a pitch between the adjacent bond pads of the chip is reduced to be smaller than the size of the solder bumps, which makes the adjacent solder bumps come into contact with each other. Such problem can be solved by RDL (redistribution layer) technology as disclosed in Taiwanese Patent No. 543125 and U.S. Pat. No. 6,455,408, etc. The RDL technology utilizes conductive circuits to redistribute the bond pads located around the chip to proper positions and then forms the UBM structure on the redistributed positions of the bond pads so as to provide a suitable pitch between the adjacent solder bumps.
FIGS. 1A to 1C show steps of a conventional redistribution process of a semiconductor device. As shown in FIG. 1A, a semiconductor substrate 10 having at least one bond pad (i.e. I/O contact) 15 is provided. A passivation layer 20 and a first dielectric layer 21 are successively formed on a surface of the semiconductor substrate 10. Next, a photoresist layer 22 having a photoresist pattern is applied on the first dielectric layer 21, and serves as a mask to define the first dielectric layer 21 and form at least one opening 23 for exposing a portion of the bond pad 15. Then, the photoresist layer 22 is removed. As shown in FIG. 1B, a first metallic layer 26 for redistribution and a second metallic layer 27 are successively formed by sputtering on the first dielectric layer 21 and in the opening 23. As shown FIG. 1C, the second metallic layer 27 is removed by etching except a predetermined redistribution area thereof that forms a UBM structure 29, and a second dielectric layer 28 is applied on the first metallic layer 26 without covering the UBM structure 29. Finally, a solder bump 31 is formed on the UBM structure 29. This completes the redistribution process for the bond pad 15.
In the above redistribution process, generally the first metallic layer 26 comprises successive laminated layers of aluminum, nickel-vanadium alloy, copper and titanium, and the second metallic layer 27 comprises successive laminated layers of aluminum, nickel-vanadium alloy and copper. During the process of etching the second metallic layer 27, as the first metallic layer 26 does not have a satisfactory step coverage effect in the opening 23, the etchant may easily penetrate the titanium layer and damage the aluminum, nickel-vanadium alloy and copper layers of the first metallic layer 26, thereby causing an electrical break of the first metallic layer 26.
When the above redistribution process is applied to a chip having a fine pitch (hereinafter referred to as “fine-pitch chip”) such as a high-speed analog product, the thickness of the first dielectric layer 21 is usually increased to reduce signal interference and thereby alters the aspect ratio of the opening 23. This not only deteriorates the step coverage effect of the first metallic layer 26 on a bottom portion of a sidewall of the opening 23, but also makes the thickness of the first metallic layer 26 on the bottom portion of the sidewall of the opening 23 reduced due to an isotropic effect of the etching process as shown in FIG. 1C, thereby easily causing the electrical break of the first metallic layer 26. Alternatively, the sidewall of the opening 23 can be slanted, which however needs an additional spacer to protect the sidewall and undesirably increases the difficulty in fabrication. Further, a slant angle of the slanted sidewall of the opening 23 has a limitation of about 65 degrees relative to a horizontal plane. If the slant angle is made smaller than 65 degrees, etching control would be hardly achieved during the process of forming the spacer.
Therefore, the problem to be solved here is to provide a semiconductor device and a fabrication method thereof, which can prevent an electrical break of a metallic layer for redistribution and can be applied to a fine-pitch chip so as to overcome the foregoing drawbacks of the prior art.